As semiconductor memory devices become more highly integrated, the size of a memory cell may be reduced. Accordingly, an area available for the memory cell capacitor and transistor is reduced. To maintain an adequate memory storage capacity, however, the capacitance for the memory cell capacitor should be maintained at an adequate level.
Various capacitor electrode structures have been suggested to maintain a desired memory cell capacitance in a smaller area. In particular, the surface area of the lower capacitor electrode has been increased by using three-dimensional structures such as cylinder or trench-type structures instead of the conventional planar electrode structure. These three-dimensional structures can thus provide an increased capacitance for a capacitor in a limited surface area of a substrate. Further increases in capacitance per unit area, however, may still be required.
Accordingly, research has been directed toward the identification of materials which can be used to form the lower electrode, the dielectric layer, and the upper electrode to further increase the capacitance per unit area of a memory cell capacitor. In particular, materials with relatively high dielectric constants have been investigated for use as the capacitor dielectric layer. For example, tantalum oxide (Ta.sub.2 O.sub.5, hereinafter referred to as "TO") layers can be used to replace conventional nitride oxide (NO) layers while providing an increased dielectric constant.
A TO layer has a relatively high dielectric constant (.epsilon.) when compared with a dielectric constant of silicon oxide (SiO.sub.2) and silicon nitride (Si.sub.3 N.sub.4). In particular, the dielectric constant of SiO.sub.2 is approximately 3.9 and the dielectric constant of Si.sub.3 N.sub.4 is approximately 7.8, while the dielectric constant of TO is approximately 24. In other words, the dielectric constant of a TO layer is approximately six times higher than the dielectric constant of a SiO.sub.2 layer and about three times higher than the dielectric constant of a Si.sub.3 N.sub.4 layer. Accordingly, a TO layer can be used to provide a dielectric layer having reduced equivalent oxide thickness (T.sub.oxeq) when compared with SiO.sub.2 or Si.sub.3 N.sub.4.
A TO dielectric layer, however, may have an increased leakage current because the band gap of TO is narrower than the band gaps of SiO.sub.2 and Si.sub.3 N.sub.4. The leakage current of a TO dielectric layer is dependent on the method used to form the capacitor including the dielectric layer. Moreover, the leakage current of a To dielectric layer is dependent in part on steps performed both before and after the formation of the TO dielectric layer. When using a TO dielectric layer, the leakage current is influenced by the following factors: (1) the properties of an interface between the lower capacitor electrode and the TO dielectric layer; (2) a reaction between the lower electrode and the TO dielectric layer; (3) oxygen defects within the TO dielectric layer; and (4) the content of carbon compounds within the TO dielectric layer. More particularly, the leakage current increases with increasing reaction between the lower electrode and the TO dielectric layer, with increased oxygen defects within the TO dielectric layer, and with increasing content of carbon compounds within the TO dielectric layer.
The increased leakage current due to oxygen defects within the TO layer and the content of the carbon compounds can be reduced by heating the TO dielectric layer at a relatively high temperature in an atmosphere including oxygen after forming the TO dielectric layer. The high temperature heating step, however, may result in a relatively thick silicon oxide layer on a silicon lower electrode due to a reaction between the TO dielectric layer and the silicon of the lower electrode. A barrier layer on the lower electrode can be used to reduce the problem of the silicon oxide layer. The use of a barrier layer on the lower electrode, however, may cause additional problems as discussed below with regard to FIGS. 1 through 3.
As shown in FIG. 1, a conductive layer 14 is used as the lower electrode of the capacitor. This conductive layer 14 is formed on an interlayer dielectric layer (ILD) 12. In addition, a conductive plug 10 through the interlayer dielectric layer 12 provides an electrical connection between a semiconductor substrate and the lower capacitor electrode. Moreover, the conductive layer 14 is an in-situ doped polysilicon layer.
A nitride layer 16 is then formed on the conductive layer 14 using a rapid thermal nitridation (RTN) step, as shown in FIG. 2. The nitride layer 16 reduces oxidation of the conductive layer 14 when a high temperature oxidation step is performed after forming the dielectric layer such as a TO dielectric layer.
As shown in FIG. 3, a TO dielectric layer 18 is formed on the nitride layer 16. Moreover, the TO dielectric layer 18 can be stabilized using a high temperature step in an atmosphere including oxygen. The formation of silicon oxide on the conductive layer 14 is reduced because the nitride layer 16 covers the conductive layer 14. A TiN layer 19 is formed on the TO dielectric layer 18, and an in-situ doped polysilicon layer 20 is formed on the TiN layer 19. The polysilicon layer 20, the TiN layer 19, the TO dielectric layer 18, and the nitride layer 16 are then patterned to complete the capacitor structure.
According to the conventional method for forming a capacitor discussed above, the nitride layer 16 which is used to reduce the oxidation of the conductive layer 14 may include silicon atoms which do not form silicon-nitrogen couplings. Oxidation of the lower capacitor electrode (conductive layer 14) during a high temperature step using oxygen following the formation of the TO layer 18 can be reduced by the nitride layer 16. It may be difficult, however, to prevent the reaction between oxygen atoms within the TO dielectric layer 18 and silicon atoms of the nitride layer 16. The TO dielectric layer 18 may thus be degraded so that the leakage current is not sufficiently suppressed.